Novel copper via filling electrolyte for plating on package substrates

The Semi Additive Process (SAP) enables very fine lines and spaces to produce highly sophisticated Integrated Circuit Substrates (ICS). When operating with lines and spaces (L/S) of 10/10 µm and less the copper thickness variation is one of the critical parameters, which must be controlled within a tight range to avoid reliability problems in assembly or during the lifetime.

The challenges and requirements for a new copper electrolyte to fill the gap between the organic IC-substrate and the semiconductor technology have increased over time with the shrinkage of the L/S and the smaller pattern features on the substrate.

During this webinar, we will highlight the requirements for next generation IC Substrate plating processes and the results of our newly developed process InPro® SAP3 such as plated copper thickness and copper thickness variation, BMV filling performance, microsection pictures and reliability results.